Bit-mapped video memory for graphics display is well-known in computer systems. For example, a bit-mapped approach to graphics display was used in the Apple II computer, manufactured during from late 1970's to the mid 1980's by Apple Computer Corp., Cupertino, Calif. Briefly, the individual storage locations of a video memory are arranged (at least in the mind of the programmer) as an array of N rows each comprising M bytes. A predetermined number of bits of each byte is associated with a unique pixel (picture element). That is, in a monochrome display, each pixel might be represented by a single bit (i.e., pixel on or off), thus data for eight pixels could be stored in a single byte. However, in a color display, each pixel would require at least 1 bit (and probably more) of color information for each of the primary colors of red, green, and blue, thus, requiring more video memory for each pixel.
Modern on-screen display controllers utilize the concept of a color palette to increase the numbers of colors available to a programmer. In order to more easily understand this concept, consider the following. When an artist is creating a painting, he uses a physical palette to hold a dab (i.e., a small portion) of each of a variety of colors which he is most likely to need in the near future. If the artist finds that he needs other colors (and if his currently-held palette is full), he must change to another palette containing the new colors. In this way, the artist does not have to have immediate access to all colors at all times. Similarly, in electronic graphics, the on-screen display integrated circuit (OSD IC) uses a palette concept to avoid having to provide immediate access to all colors at all times. In the palette approach a pixel color is defined by four bits which form an address which, in turn, points to one of sixteen color-storage locations on the palette. Each location on the palette stores data indicating the amount of red (R), green (G), and blue (B) which make up a particular color. For example, each color stored in each of the sixteen locations on the palette may comprise twelve bits, four bits for red, four bits for green, and four bits for blue. If the programmer finds that he needs yet another (i.e., seventeenth) color, then he must reload his palette with data defining the different desired colors. In this way, VRAM memory space is conserved in that only 4 bits/pixel are used to define a palette location holding particular color data, rather than 12 bits/pixel to define a particular pixel color directly.
Unfortunately, the above-noted memory saving must be paid for at the expense of the time in which it takes to reload the color palette, and to load the OSD IC with other necessary control data. Typically, prior art OSD ICs used memory mapped registers to hold color palette and control data. These registers were written-to, by a control microprocessor, as if they were memory locations, and they did indeed logically occupy those locations, often creating unwanted "holes" in memory (i.e., discontinuities in the memory address space). These "holes" can be particularly troublesome when large blocks of contiguous memory locations are needed to hold graphics information.
Graphics data are written to the VRAM by the control microprocessor via a parallel port in a direct access fashion, but are read out to the OSD chip via a higher speed serial port. Graphics displays use a relatively large amount of video memory (VRAM), typically 1 Mbit 4-Mbits (128 kbytes-512 kbytes) in size. It requires a total of 17 to 19 address lines to uniquely address an 8-bit memory location within memory chips this large. In order to limit the physical size of the VRAM chip, it is commonplace in VRAM to limit the number of address pins to a lesser number, such as 9, and to time-multiplex the address lines. Such a VRAM is the M5M482128ATP, manufactured by Mitsubishi Corp. Because of the multiplexing of the address lines, the time it takes to address a particular byte in a 1-Mbit VRAM is extended because it takes two transfers of address data (i.e., A16-A8 (9 bits) followed by A7-A0 (the remaining 8 bits)) before a read or write can be done at any location. This extension of time becomes significant when one considers that the amount of control data and palette data to be transferred may total as much as 48 bytes, with each transfer taking approximately 400 nanoseconds (ns) per byte, for a total of approximately 19.2 microseconds (.mu.s) during which time the control microprocessor is excluded from the system bus. This is especially significant when one realizes that this data is typically transferred to the OSD IC during each television vertical interval, when the control microprocessor also needs access to the system bus to load the VRAM with graphics data for the next active video display.